1. Field of the Invention
The present invention relates to a circuit arrangement comprising a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions for the purpose of reducing the redundancy in the image signals.
2. Description of the Prior Art
The digital transmission of color picture signals via the channels of the pulse code modulation (PCM) hierarchy of a transmission network requires a data reduction by reducing the sampling frequency for reasons of the nature of the appertaining transmission channels. A respectively required codec therefore requires digital filters for decimation or, respectively, interpolation. Horizontally or, respectively, vertically adjoining image dots, referred to below as orders 0.sub.0, 0.sub.1 . . . 0.sub.6, must be binarily weighted and added in the filters (cf. FIG. 1). Six scanning lines must be kept ready in line memories to this end for filtration in the vertical direction.
Digital filters of this type for a test system on the basis of standard modules have already been realized. Static CMOS-RAMs are employed therein for the realization of the required line memories, whereby the access to the line memory cells occurs by incrementing a counter and decoding the counter reading. An arithmetic unit required for such digital filters is composed of cascaded adders and registers. The space requirement and the expenses are relatively high given such a construction. The data rates which can be achieved are limited by the cycle time of the static memory cells which are disadvantageous. Moreover, the memory access via a decoder, given the cyclical operating mode required in the present case is involved and, therefore, inefficient. Finally, an integration of this solution is not particularly suitable because of the irregularity of the resulting circuit structure.